Class project deliverables (ECE6502 ASIC/SoC Design)

Project: Make Based Flow Engineering for Chip Design

The purpose of this project is to utilize a tool called "make" to automate the chip design flows. While it still has a long way to go to be seriously called a "flow generator", the project at least shows:

1. Make can be used to automate complex flow

2. How a flow generator should look like

There are two directories and one document besides this readme file:

./flow_generator: the source of a minimalist working flow generator based on the "Mickey_Mouse" flow, showing the basic framework. Check ./flow_generator/readme for more information.

./make_clp: make automated IBM chartered 90nm tech Cadenece low power flow (frontend). Check ./make_clp/readme for more information.

./asic_final_slides.pdf: final presentation slides of this class project.


The project homepage is at http://venividiwiki.ee.virginia.edu/twiki/bin/view/Main/Flow. 

